The present invention relates to a technology of manufacturing semiconductor devices, and particularly to a technology which can be effectively applied to a step of mounting a semiconductor chip over a wiring substrate.
Japanese Patent Laid-Open No. 2002-190488 (Patent Document 1) describes a semiconductor device which mounts a semiconductor chip over a wiring substrate, and in which a wiring conductor pattern and a dummy conductor pattern laid in a region other than the region having the wiring conductor pattern laid therein are provided.
Japanese Patent Laid-Open No. 2008-218848 (Patent Document 2) describes a semiconductor device which mounts a semiconductor chip over a wiring substrate via an adhesive film, and in which a real wiring pattern and a dummy pattern are provided in a chip-mounting region of the wiring substrate.
There is a mounting technology that uses a paste-like adhesive material (die bonding material), as a manufacturing technology of a semiconductor device having a semiconductor chip mounted over a wiring substrate. Inventors of the present invention have examined the technology of mounting a semiconductor chip over a wiring substrate via the paste-like adhesive material and found the following problems.
As a semiconductor device becomes thinner, semiconductor chips to be mounted on a wiring substrate also tend to be thinner. If an excessive amount of the paste-like adhesive material is used when mounting such a thin semiconductor chip over a wiring substrate, a part of the adhesive material running over the circumference of the semiconductor chip may crawl up to the surface of the semiconductor chip (the opposite side of the surface facing the wiring substrate). As a countermeasure thereof, reducing the amount of the adhesive material used may be considered. However, a plurality of wirings is formed on the upper surface of the wiring substrate (the surface on which the semiconductor chip is mounted), the flatness of the upper surface is low because there exist regions where the pitch between adjacent wirings is uneven. Accordingly, it has become clear that a void (gap) occurs between the semiconductor chip and the wiring substrate because wettability (filling property) of the adhesive material between the semiconductor chip and the wiring substrate is low (poor).
Next, inventors of the present application have examined enhancement of the flatness of the wiring substrate by forming a dummy pattern in the upper surface of the wiring substrate, as described in the patent documents 1 and 2. As a result, it has been confirmed that the flatness of the upper surface of the wiring substrate can be improved by providing a dummy pattern in contrast to the case where no dummy pattern is provided. However, as described above, recent semiconductor chips are much thinner than those at the time when the above patent documents were filed, and accordingly the amount of the adhesive material used is further reduced. Consequently, with the manufacturing method of semiconductor device as described above, it has become clear that occurrence of a void cannot be completely suppressed by simply forming a dummy pattern over the wiring substrate.
The present invention has been made in view of the above circumstances and provides a technology that can suppress occurrence of a void when mounting a semiconductor chip over a wiring substrate via a paste-like adhesive material.
The above and other objects and new features of the present invention will become clear from the description of the specification and accompanying drawings.